This invention relates to segmentation of memory arrays and, in particular, to segmentation of nonvolatile memory arrays such as electrically-erasable, electrically-programmable, read-only-memories (EEPROMs). In particular, this invention relates to a segmented array architecture having buried-bitline, segment-select transistors, having remote wordline decoders, and having segment decoders.
The speed of access to information contained in non-volatile memory arrays is largely dependent on the capacitance of the bitlines and the wordlines. Those capacitances are a function of choices that include the lengths of the bitlines and wordlines, pitch, chip/bar size and aspect ratio, and process parameters. In general, small capacitances are required for fast access time during operation of memory arrays. Conventional segmentation with separate driver circuitry for each segmented wordline and for each segmented bitline is generally impermissible because that method of reducing the access time delay requires an unacceptable increase in driver circuit area on integrated circuit chips.
Increased component density in memory arrays has led to higher bitline capacitance. One way of decreasing that capacitance has been to segment the bitlines of arrays. Segmentation of bitlines of a memory array is described in U.S. patent application Ser. No. 07/402,402, filed Sep. 5, 1989 (issued Jun. 11, 1991 as U.S. Pat. No. 5,023,837) and also assigned to Texas Instruments Incorporated.
In high-density, flash-erase-type EEPROMs, reduced wordline pitch and an increased number of voltages applied to the wordlines have created difficulty in laying out the rather complicated wordline decoder and other control circuits efficiently. A need has arisen for a segmented array that allows a fewer number of wordline decoders, which are remotely located from the wordlines and which have a more-sophisticated design.